A metal insulator semiconductor (MIS) photodetector is formed by disposing a layer of nonconducting dielectric insulating material between a photosensitive semiconductor material and a metal conductor or gate. A voltage impressed across the dielectric layer results in the formation of a depletion region or MIS well within the semiconductor material which defines a capacitive element. The capacitance of this element is variable in response to photons that enter the lattice of the semiconductor layer. The measurement of this capacitance and the variance thereof provides a method for measuring the number of photons received on a given surface. These elements are normally arranged in an array with each element of the array constituting a pixel. All of the pixels are individually addressable to provide an output signal corresponding to the light impinging thereon. The operation and fabrication of arrays of this type are discussed in more detail in co-pending application Ser. No. 528,207, filed Aug. 31, 1983.
The fabrication of MIS devices heretofore has required the formation of a combined layer of semiconductor material and a layer of insulating dielectric with a metal conductive pad formed on the upper surface thereof. This metal conductive pad is the MIS gate and is semitransparent, such that impinging photons penetrate therethrough to enter the depletion region of the semiconductor material and free lattice electrons therein.
To ensure that a sufficient number of photons enter the depletion region, the semitransparency of the gate and the dielectric layer is a major factor and presents manufacturing and device design problems. One solution to this problem has been to fabricate the MIS device with the layer of photosensitive semiconductor material disposed as a superstrate with respect to the array. The MIS gate is formed with a metal pad disposed beneath the semiconductor layer and bonded to a dielectric insulating layer of the superstrate. The thickness of the semiconductor layer is then reduced to allow photons to enter the depletion region through the top of the superstrate without having to pass through the gate. Fabrication of MIS gates onto the semiconductor/insulator superstrate requires metal deposition and photolithographic patterning techniques which expose the sensitive superstrate materials to potentially damaging mechanical, thermal and ultraviolet radiation stresses. Subsequent mating of patterned superstrate to patterned substrate is a critical and difficult process requiring a large number of high quality ohmic contacts to be made between the substrate circuitry and the superstrate gates. This process presents considerable difficulties.
In view of the above disadvantages, there exists a need for an improved configuration of an MIS array which eliminates passage of the detected photons through the MIS gate and facilitates contact therewith and reduces the risk and difficulty of processing.